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System-On-A-Chip verification methodology and techniques /
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101206s2002 mau s j eng d |
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|a9780306469954 (electronic bk.)
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|a9780792372790 (paper)
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|aQA76.9.S88|bR37 2002|cR224
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|a621.395|221
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|aQA76.9.S88|bR224 2002
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|pEB|dQA76.9.S88|eR224|y2002
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|aRashinkar, Prakash.
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|aSystem-On-A-Chip verification|h[electronic resource] :|bmethodology and techniques /|cPrakash Rashinkar, Peter Paterson, Leena Singh.
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|aBoston, MA :|bKluwer Academic Publishers,|cc2002.
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|axx, 372 p. :|bill., digital ;|c25 cm.
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|aComputer software|xDevelopment.
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|aElectronic digital computers|xDesign and construction.
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|aSystem design.
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|aPaterson, Peter.
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|aSingh, Leena.
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|aSpringerLink (Online service)
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|tSpringer e-books
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|uhttp://dx.doi.org/10.1007/b116428
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|aComputer Science
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